Device for Detecting and Illuminating the Vasculature Using an FPGA

ABSTRACT

A laser based vascular illumination system utilizing a FPGA for detecting vascular positions, processing an image of such vasculature positions, and projecting the image thereof onto the body of a patient.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 14/723,674, filed on May 28, 2015, which is a continuation of U.S. application Ser. No. 13/957,767, filed on Aug. 2, 2013, now issued as U.S. Pat. No. 9,072,426, which claims priority on U.S. Provisional Application Ser. No. 61/678,726, filed on Aug. 2, 2012, with the disclosures of each incorporated herein by reference.

BACKGROUND Summary

A laser based vascular illumination system utilizing a FPGA for detecting vascular positions, processing an image of such vasculature positions, and projecting the image thereof onto the body of a patient.

BRIEF DESCRIPTION

FIG. 1 Block diagram of a system for detecting and illuminating the vasculature in a patient.

FIG. 2 Shows the signal processing flow of the FPGA.

FIG. 3 shows the internal bus architecture of the FPGA.

FIG. 4 shows details of the vein processing.

FIG. 5 shows the vein processing at the boundary of the image frames.

FIG. 6 shows further detail of the vein processing at the boundary of the image frames.

FIG. 7 2-D Moving Window Sum Generator.

FIG. 8 shows a X-sum generator.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of a system for detecting and illuminating the vasculature in a patient.

The system shown in the block diagram of FIG. 1 is used for detecting the location of veins on a patient and illuminating the veins.

The disclosures of U.S. patent application Ser. No. 12/804,506, now issued as U.S. Pat. No. 8,463,364 are incorporated herein by reference.

In a preferred embodiment, FIGS. 30-47 of application Ser. No. 12/804,506 illustrates an assembly of a housing that may be used in the present invention. In the present invention, circuit boards 43, 44 and 15 of application Ser. No. 12/804,506 may be modified to contain the circuitry described by the block diagram in FIG. 1. The remainder of the device in FIGS. 30-47 can remain substantially the same.

In FIG. 1 an FPGA 1 (field programmable gate array) is configured to control a red laser drive 2 which in turn drives a red laser 3. The output of the red laser 3 is controlled in a manner so as to illuminate the detected veins. A red laser feedback 4 detects the output of the red laser 3 and sends the information to the FPGA 1. Accordingly, a closed loop is formed whereby the FPGA 1 can both drive the Red laser 3 and receive feedback as to the red laser 3 state.

FPGA 1 outputs data to an IR laser drive 5 which in turn drives an IR laser 6. The output of the IR laser 6 is controlled to output an intensity of IR light, aimed at the area of the body where veins are located, sufficient to detect the veins. An IR laser feedback 7 detects the output of the IR laser 6 and sends the information to the FPGA 1. Accordingly, a closed loop is formed whereby the FPGA 1 can both drive the IR Laser 6 and receive feedback as to the IR laser 6 state.

FPGA 1 communicates to both a x-mirror drive 8 and a y-mirror drive 9 to drive x-mirror 10 and y-mirror 11 in such a manner that a raster pattern is formed on the patient when the Red laser 3 and the IR laser 6 are coaxially projected thereon. X-mirror feedback 12 and y-mirror feedback 13 detect the positions of the x-mirror 10 and y-mirror 11, respectively, and communicates such information to the FPGA1.

Top photodiode 23 and bottom photodiode 22 receive the IR Laser 6 reflected off the patient, converts the light into an analog signal which is provided to Top FE 25 and Bottom FE 24, and then to Top ADC 27 and bottom ADC 25, respectively. The top FE 25 and the bottom FE 24 are front end circuits that provide analog filtering, gain control and threshold of the analog signals. The Top ADC 27 and bottom ADC 26 are analog to digital converters that convert the analog signals to digital representations thereof to be communicated to the FPGA 1. Control lines are provided from the FPGA 1 to the top FE 25 and the bottom FE 24 to set parameters such as, for example, gain control and analog filtering.

From a mechanical standpoint, the red laser 3 and the IR laser 6 are co axially aligned and projected off of mirrors X-mirror 10 and Y-mirror 11 to form a pattern, such as for example, a raster pattern on the patient. The IR laser 6 reflects off the patient and is received by top photodiode 23 and photodiode 22. The reflected IR light contains information as to the location of the veins (IR light is absorbed by the blood in the veins and therefore the amount or reflected IR light is lower when the IR laser 6 is aimed at a vein. The FPGA 1 time sequentially receives in the signal form the top ADC 27 and the bottom ADC and can form two partial and/or full frame images of the reflected IR light (hereinafter a top channel data and a bottom channel data wherein the top channel data is received from the top ADC 27 and the bottom channel data is received from the bottom ADC). The FPGA 1 processes one or both of the partial and/or full image to detect and enhance the image of the veins. The enhanced image is time sequentially projected by the Red laser 3 onto the patient.

A CPLD is provided for controlling an LCD 19 with displays user information related to the operating status of the device. It also controls an audio 20 output to provide audible tones to the user. Finally the CPLD 18 controls the switches 21 on the unit for turning on and off the units as well as selecting user modes and entering data.

A microprocessor PIC MCU 17 is provided for receiving and monitoring the IR laser feedback 7 signal, the red laser feedback 4 signal, the x-mirror feedback 12 signal and the y-mirror feedback 13 signal. Since these signals are also provided to the FPGA 1, redundancy monitoring of the signals is provided by the PIC MCU 17. This is particularly important when regulatory requirements require redundant monitoring of the laser power and movement to comply with safety requirements. The PIC MCU 17 also monitors the device power management 14, the Li-ion Battery management 15 circuitry and the Li-ion Fuel gauge 16.

FIG. 2 shows an example of the signal processing flow of the FPGA.

FIG. 2 shows an embodiment of the signal processing algorithm of the FPGA of FIG. 1. As described with reference to FIG. 1, the image of the reflected IR laser 6 is time sequentially stored in the FPGA 1 as top channel data 30T and bottom channel data 30B.

The X-mirror 10 oscillates about a single axis to move the laser beam from the IR laser 6 to form a line. The beam moves first in one direction and then back in the other direction. It is critical that the left to right image data be in convergence with the right to left data. The top line correlator 31T measures the shift in the convergence of the top channel data 30T and supplies the information to the mirror convergence control 34. Similarly, the bottom line correlator 31B measures the shift in the convergence of the bottom channel data 30B and supplies the information to the mirror convergence control 34. The mirror convergence control 34 can adjust the control signals provided from the FPGA 1 to the x-mirror drive 8 so as to converge the data.

A top histogram 32T receives the top channel data 30T and generates a histogram based upon an entire frame of the top channel data 30T. Similarly, a bottom histogram 32B receives the top channel data 30B and generates a histogram based upon an entire frame of the bottom channel data 30B. The histograms contain information describing the characteristics of the images, including but not limited to contrast and intensity levels. The top histogram 32T and the bottom histogram 32B are provided to exposure control 35. Exposure control 35 communicates appropriate signals the IR laser drive 5 to adjust the power of the IR laser 6 on a frame by frame basis until the histograms indicate appropriate images. The exposure control 35 also communicates with the top FE 25 and bottom FE 24 to adjust parameters such as setting thresholds and setting electrical gain.

A top vein processing 33T block receives the top channel data 30T and performs image processing to detect vein patterns and provides the enhanced vein image to fused vein projection 36. Similarly, bottom vein processing 33B block receives the bottom channel data 30B and performs image processing to detect vein patterns and provides the enhanced vein image to fused vein projection 36. The fused vein projection 36 forms a single image and communicates the image to the alpha blended projection 38. The fused vein projection 36 can form the single image by merging the images from the top vein processing 33T and bottom vein processing 33B. Alternative, the fused vein projection 36 can simply select the best image received from the top vein processing 33T and the bottom vein processing 33B.

Alpha channel 37 forms an image that contains graphical data, such as text or characters. Alpha channel 37 and fused vein projection 36 are provided to alpha blended projection 38 with drives the IR laser drive 5 to display an image which is the combination of the fused vein projection 36 and the alpha channel 37.

FIG. 3 shows an example of the internal bus architecture of the FPGA

FIG. 4 shows details of the top vein processing 33T and bottom vein processing 33B.

FIG. 5 shows the vein processing at the boundary of the image frames.

FIG. 6 shows further detail of the vein processing at the boundary of the image frames.

FIG. 7 shows the 2-D Moving Window Sum Generator.

FIG. 8 shows a X-sum generator. 

What is claimed is:
 1. An image capture device configured to detect, process, and project an image using a field programmable gate array (FPGA), said image capture device comprising: a first layer configured to output a beam of light as an infrared wavelength; a second laser configured to output a beam of light at a visible red wavelength; a combiner configured to combine said beams of light from said first and second lasers into a co-axial beam of light; an x-direction mirror configured to reflect said coaxial beam of light, and to be pivotable about a first axis, in a first direction and in a second direction; an x-direction mirror driver configured to drive said x-direction mirror to oscillate about said first axis, to cyclically reflect said coaxial beam of light in a line, in both said first and second directions; a y-direction mirror configured to reflect said line of light received from said x-direction mirror, and to be pivotable about a second axis, in a third direction and a fourth direction; a y-direction mirror driver configured to drive said y-direction mirror to oscillate about said second axis; wherein said FPGA is configured to control said x-direction mirror driver and said y-direction mirror driver to control said oscillations about said first and second axes to form a pattern of said red and infrared wavelengths of light; a feedback means configured to detect a position of said x-direction mirror and said y-direction mirror, and to signal said positions to said FPGA; a photodiode configured to receive the image formed from said infrared light, said photodiode further configured to convert the received image into an analog signal; wherein said second laser driver is further configured to receive said analog signal, and to drive said red laser to project the image using said analog signal; a line correlator configured to measure a shift in convergence between said line of light in said first direction and said second direction, for each said oscillation of said X-direction mirror; a mirror convergence control configured to receive said measured shift in convergence from said line correlator, and to adjust said control of said first mirror driver by said FPGA, for said line in said first direction to converge with said line in second direction.
 2. The image capture device according to claim 1, further comprising: a second feedback means, said second feedback means configured to detect said output of said first and second lasers, and to signal said detected output to said FPGA, for said FPGA to control said output of said first and second lasers.
 3. The image capture device according to claim 2, further comprising: an analog-to-digital converter configured to receive said analog signal from said photodiode, and to convert said analog signal into a digital image signal, and to communicate said digital image signal to said FPGA; wherein said FPGA is configured to receive and process said digital image signal and to output a processed image signal; and wherein said second laser driver is further configured to receive said processed image signal from said FPGA, and to drive said red laser to project said processed image using said x-direction mirror and said y-direction mirror.
 4. The image capture device according to claim 3, wherein said photodiode comprises a top photodiode and a bottom photodiode each configured to receive a full frame of the image and to output a respective said analog signal.
 5. The image capture device according to claim 4, further comprising: a top front end circuit and a bottom front end circuit, each configured to respectively receive said analog signals of said top and bottom photodiodes; said top and bottom front end circuits contoured to control analog filtering, gain, and threshold of said respective analog signals; wherein said analog-to-digital converter comprises a top analog-to-digital converter (ADC) and a bottom ADC configured to respectively receive said analog signals from said top and bottom front end circuits, and to convert said analog signals into respective digital image signals, and to communicate said respective digital image signals to said FPGA; said FPGA further configured to receive each of said respective digital image signals from said top and bottom ADC, and to perform imaging processing within each of said respective images, to form respective enhanced images; wherein said FPGA is further configured to form a single enhanced image signal from said respective enhanced images; and wherein said second laser driver is further configured to receive said single enhanced image from said FPGA, and to drive said red laser to project said enhanced single image using said x-direction mirror and said y-direction mirror.
 6. The image capture device according to claim 5, wherein said single enhanced image is formed from: a merged signal formed by merging said respective digital image signals; or a selected best image signal selected from either of said respective digital image signals.
 7. The image capture device according to claim 5, further comprising: a top histogram generator and a bottom histogram generator, each of said top and bottom histogram generators configured to generate a respective histogram of characteristics of said analog signals from said top and bottom photodiodes; and wherein said FPGA is further configured to receive and use said respective histograms to signal said infrared laser driver to adjust power to said infrared laser on a frame by frame basis until said histograms indicate a proper image.
 8. The image capture devise according to claim 7, wherein said histogram characteristics comprise contrast and intensity levels.
 9. The image capture device according to claim 7, further comprising a CPLD configured to control an LCD to display an operating status of said system thereon.
 10. The image capture device according to claim 9, wherein said CPLD is further configured to control an audio output to provide audible tones to a user.
 11. The image capture device according to claim 10, wherein said CPLD is further configured to control one or more switches on said system for turning on and off said system, for selecting one or more user modes, and for entering data therein.
 12. The image capture device according to claim 2, further comprising a microprocessor configured to redundantly receive and monitor said feedback signal for said first and second lasers, and said feedback signal for said X-direction mirror and Y-direction mirror, in conjunction with said FPGA.
 13. An image capture device comprising: means for outputting and scanning a beam of light comprising an infrared wavelength and a visible red wavelength in a first and a second direction, for forming respective lines in said first and second directions, and for scanning said lines in a third direction and a fourth direction; a field programmable gate array (FPGA) configured to control said means for outputting and scanning to control said scanning in said first and second directions, and to control said scanning in said third and fourth directions, to form a pattern; a photodiode configured to receive an image formed from said scanned pattern of said infrared wavelength of light, said photodiode further configured to convert the image into an analog signal; wherein said means for outputting and scanning is further configured to receive said analog signal, and to scan said image using said visible red wavelength; a line correlator configured to measure a shift in convergence between said respective lines in said first and second directions; a mirror convergence control configured to receive said measured shift in convergence from said line correlator, and to adjust said control of said means for outputting and scanning by said FPGA, for said line in said first direction to converge with said line in said second direction.
 14. The image capture device according to claim 13, further comprising; a second feedback means configured to detect said output of said means for outputting and scanning, and to signal said detected output to said FPGA, for said FPGA to control said output of said means for outputting and scanning; an analog-to-digital converter configured to receive said analog signal from said photodiode, and to convert said analog signal into a digital image signal, and to communicate said digital image signal to said FPGA; wherein said FPGA is configured to receive and process said digital image signal and to output a processed image signal; and wherein said means for outputting and scanning is further configured to receive said processed image from said FPGA, and to scan said processed image using said red wavelength.
 15. The image capture device according to claim 13, wherein said photodiode comprises a top photodiode and a bottom photodiode each configured to receive a full frame of said image and to output a respective said analog signal.
 16. The image capture device according to claim 15, further comprising: a top front end circuit and a bottom front end circuit, each configured to respectively receive said analog signals of said top and bottom photodiodes; said top and bottom front end circuits configured to control analog filtering, gain, and threshold of said respective analog signals; wherein said analog-to-digital converter comprises a top analog-to-digital converter (ADC) and a bottom ADC configured to respectively receive said analog signals from said top and bottom front end circuits, and to convert said analog signals into respective digital image signals, and to communicate said respective digital image signals to said FPGA; said FPGA further configured to receive each of said respective digital image signals from said top and bottom ADC, and to perform imaging processing within each of said respective images, to form respective enhanced images; wherein said FPGA is further configured to form a single enhanced digital image from said respective enhanced images; and wherein said means for outputting and scanning is further configured to receive said single enhanced image front said FPGA, and to scan said single enhanced image using said visible red wavelength.
 17. The image capture device according to claim 16, wherein said single enhanced image comprises: a merged signal formed by merging said respective digital image signals; or a selected best image signal selected from either of said respective digital image signals.
 18. The image capture device according to claim 16, further comprising: a top histogram generator and a bottom histogram generator, each of said top and bottom histogram generators configured to generate a respective histogram of characteristics of said analog signals from said top and bottom photodiodes; and wherein said FPGA is further configured to receive and use said respective histograms to adjust power to said means for outputting and scanning on a frame by frame basis until said histograms indicate a proper image.
 19. The image capture device according to claim 18, wherein said histogram characteristics comprise contrast and intensity levels.
 20. The image capture device according to claim 13, further comprising a microprocessor configured to redundantly monitor and control said means for outputting and scanning to control said scanning in said first and second directions, and said scanning in said third and fourth directions, to form a raster pattern.
 21. An image capture device comprising: means for outputting and scanning a beam of light comprising an infrared wavelength and a visible red wavelength in a first and a second directions, for forming respective lines in said first and second directions, and for scanning said lines in a third direction and a fourth direction; an electronic component configured to control said means for outputting and scanning to control said scanning in said first and second directions, and to control said scanning in said third and fourth directions, to form a pattern; a photodiode configured to receive an image formed from said scanned pattern of said infrared wavelength of light, said photodiode further configured to convert the image into an analog signal; wherein said means for outputting and scanning is further configured to receive said analog signal, and to scan said image using said visible red wavelength; a line correlator configured to measure a shift in convergence between said respective lines in said first and second directions; a mirror convergence control configured to receive said measured shift in convergence from said line correlator, and to adjust said control of said means for outputting and scanning by said electronic component, for said line in said first direction to converge with said line in said second direction.
 22. The image capture device according to claim 21, further comprising: a second feedback means configured to detect said output of said means for outputting and scanning, and to signal said detected output to said electronic component, for said electronic component to control said output of said means for outputting and scanning; an analog-to-digital converter configured to receive said analog signal from said photodiode, and to convert said analog signal into a digital image signal, and to communicate said digital image signal to said electronic component; wherein said electronic component is configured so receive and process said digital image signal and to output a processed image signal; and wherein said means for outputting and scanning is further configured to receive said processed image from said electronic component, and to scan said processed image using said red wavelength.
 23. The image capture device according to claim 22, wherein said photodiode comprises a top photodiode and a bottom photodiode each configured to receive a full frame of said image and to output a respective said analog signal. 